In a typical disk drive system, gross timing is maintained by the spin control servo system. This system usually achieves better than 1% tolerance. When the drive is operating at the nominal spin rate, the data clock (PLLCLK, extracted from the data stream) will be in exact frequency lock with the crystal based reference frequency (REFCLK). As a check on the accuracy of the spin control servo, one can monitor the difference between the data clock and the crystal clock. Loss of frequency lock is defined in terms of frequency drift per unit time.
Another more important reason to monitor the frequency difference between PLLCLK and REFCLK is so that one can detect when the PLLCLK is incorrectly locking on the data stream. This can occur if disk orientation is lost or if there are sufficient errors in the data stream to cause the PLL (phase locked loop) to lock on the wrong frequency. When frequency synchronization between the PLLCLK and the data stream is lost, errors are introduced into the decoded data stream, which the error correction code (ECC) must correct. Therefore, it is imperative to regain synchronization as soon as possible.
During initial lock, the PLL should be locking on the data stream. Gain should be set to HIGH and Mode should be set to PHASE/FREQUENCY. After Lock is acquired, the Gain should be set LOW and the Mode set to PHASE ONLY. While Device Read Gate (DRG) is still asserted, the input selector should remain selecting the data stream. When DRG is de-asserted, the Input Select should be switched to the Reference Frequency (REFCLK).
At times, the data stream may fall out of lock with the reference frequency. When this occurs, re-lock must be accomplished quickly in order to minimize the amount of data requiring correction. Re-lock can generally be accomplished by selecting the Reference Frequency with the Input Select, setting the Mode to PHASE/FREQUENCY and the Gain to HIGH. After an appropriate amount of time, the PLL input should be switched back to the data stream and the Mode set to PHASE ONLY. After running with these settings for a period of time, the PLL can be returned to LOW Gain. (The foregoing mnemonics, control settings, etc. set out in capital letters are well known in the relevant art, and therefore are not specifically defined herein.)